The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely sophisticated devices that may be found in many different settings. Computer systems typically include a combination of hardware (e.g., semiconductors, circuit boards, etc.) and software (e.g., computer programs). As advances in semiconductor processing and computer architecture push the performance of the computer hardware higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
One technique for increasing the power of computer systems is often referred to as symmetric multiprocessing (SMP), which is an architecture in which multiple processors share the same memory. One of the processors typically loads the operating system, which brings the other processors online. The operating system uses the multiple processors as a pool of processing resources, all executing simultaneously, either processing data or in an idle loop waiting for a task to execute.
One advantage of SMP systems is scalability, in that as the need for processing power increases, additional processors may be added. A second advantage is high availability or fault resistance, in that clusters of two or more SMP systems may be used, where if one SMP system fails, the others continue to operate. A third advantage of SMP systems is performance, in that SMP speeds up whatever processes can be overlapped. For example, in a desktop computer, SMP can speed up the running of multiple applications simultaneously. If an application is multithreaded, which allows for concurrent operations within the application itself, then SMP can improve the performance of that single application.
Many of today's scalable multi-processor (SMP) systems use the idea of multi-processor nodes (consisting of one or more processors attached to a control/dataflow chipset) interconnected by some form of scalability fabric, such as a serial interconnection. Certain SMP-capable processors used in these systems possess the ability to send inter-processor interrupts to one or more processors logically grouped into clusters on the local node or on remote nodes. These processors also typically transmit information related to the priority level of the task(s) currently running on a given process or thread, which can in turn be used to determine redirection of interrupts to the lowest-priority threads, in order to not impact the performance of high-priority threads. To further complicate matters, a set of processors may be clustered such that not all members of a cluster are resident on one physical node. The problem with this scenario is that without prior knowledge of how these processor groups are organized across node boundaries, interrupts and task priority information must be broadcast to all remote nodes, as well as to the local node, for further processing. Not only does this broadcasting waste valuable scalability bandwidth, but it also forces each node to maintain a relatively large database of all possible combinations of group/cluster identifiers, processor identifiers, home nodes, and task priority levels for all processors in the system. This creates substantial hardware implementation cost for each node in the system, and this problem is likely to grow linearly with the increasing size of such SMP systems.
Thus, a technique is needed to decrease the cost of nodes in a multi-processor system.